H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 402

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 I/O Ports
9.8.2
Table 9.13 shows the port A register configuration.
Table 9.13 Port A Registers
Notes: 1. Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit
Initial value
R/W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Rev. 3.00 Sep 15, 2006 page 368 of 988
REJ09B0330-0300
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register *
Port A open-drain control register *
Modes 1 to 3, and 7 *
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to
PA0DDR.
Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address
output, while clearing the bit to 0 makes the pin an input port.
2. Only applies to the H8S/2351.
Register Configuration
:
:
:
PA7DDR
W
7
0
PA6DDR
W
6
0
2
2
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
PA5DDR
W
5
0
PA4DDR
W
4
0
R/W
W
R/W
R
R/W
R/W
PA3DDR
W
3
0
H'00
H'00
H'00
Initial Value
H'00
Undefined
PA2DDR
W
2
0
PA1DDR
W
1
0
H'FF59
Address *
H'FEB9
H'FF69
H'FF70
H'FF77
PA0DDR
W
0
0
1