H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 290
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 290 of 1025
- Download datasheet (6Mb)
Section 7 DMA Controller (DMAC)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit
is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to
the CPU or DTC.
Figure 7.15 shows the operation flow in block transfer mode.
Rev. 3.00 Sep 15, 2006 page 256 of 988
REJ09B0330-0300
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