H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 206
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 206 of 1025
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Section 6 Bus Controller
RAS up mode: To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to
DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.22 shows an example of the
timing in RAS up mode.
In the case of burst ROM space access, the RAS signal is not restored to the high level.
6.5.11
The H8S/2350 Group is provided with a DRAM refresh control function. Either of two refreshing
methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing.
(1) CAS-before-RAS (CBR) Refreshing
To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in
DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is
Rev. 3.00 Sep 15, 2006 page 172 of 988
REJ09B0330-0300
CAS, LCAS
Note: n = 2 to 5
CSn (RAS)
D
A
15
23
Refresh Control
to D
to A
0
0
Figure 6.22 Example of Operation Timing in RAS Up Mode
T
p
DRAM access
T
r
T
c1
T
c2
DRAM access
T
c1
T
c2
External space
T
1
access
T
2
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