H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 227

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.11.4
External Bus Release Usage Note
External bus release can be performed on completion of an external bus cycle. The RD signal,
DRAM interface RAS and CAS signals remain low until the end of the external bus cycle.
Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change
from the low level to the high-impedance state.
6.12
Resets and the Bus Controller
In a power-on reset, the H8S/2350, including the bus controller, enters the reset state at that point,
and an executing bus cycle is discontinued.
In a manual reset, the bus controller’s registers and internal state are maintained, and an executing
external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is
initialized by a manual reset, DACK and TEND output is disabled and these pins become I/O
ports controlled by DDR and DR.
Rev. 3.00 Sep 15, 2006 page 193 of 988
REJ09B0330-0300