H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 280
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 280 of 1025
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Section 7 DMA Controller (DMAC)
7.5.5
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCR to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR.
Table 7.9 summarizes register functions in single address mode.
Table 7.9
Legend:
MAR:
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
DACK: Data transfer acknowledge
Note:
MAR specifies the start address of the transfer source or transfer destination as 24 bits.
IOAR is invalid; in its place the strobe for external devices (DACK) is output.
Rev. 3.00 Sep 15, 2006 page 246 of 988
REJ09B0330-0300
Register
23
* See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode,
Memory address register
Single Address Mode
15
and 7.5.4, Repeat Mode.
Register Functions in Single Address Mode
MAR
ETCR
DACK pin
0
0
DTDIR = 0
Source
address
register
Write
strobe
Transfer counter
Function
DTDIR = 1
Destination
address
register
Read
strobe
Initial Setting
Start address of
transfer destination
or transfer source
(Set automatically
by SAE bit; IOAR is
invalid)
Number of
transfers
Operation
*
Strobe for
external device
*
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