H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 166

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.2.4
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for areas 2 to 5 and area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface. In normal mode, the selection can be made from the entire external space.
Rev. 3.00 Sep 15, 2006 page 132 of 988
REJ09B0330-0300
Bit 7
ICIS1
0
1
Bit 6
ICIS0
0
1
Bit 5
BRSTRM
0
1
Bit
Initial value
R/W
Bus Control Register H (BCRH)
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
:
:
:
ICIS1
R/W
7
1
ICIS0
R/W
6
1
BRSTRM
R/W
5
0
BRSTS1
R/W
4
1
BRSTS0
R/W
3
0
RMTS2
R/W
2
0
RMTS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
RMTS0
R/W
0
0