H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 10
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 10 of 1025
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Rev. 3.00 Sep 15, 2006 page x of xxxiv
Item
12.3.3 Timing of
Setting Overflow Flag
(OVF)
Figure 12.6 Timing of
Setting of OVF
13.2.8 Bit Rate
Register (BRR)
Table 13.3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
14.1 Features
14.2.2 Serial Status
Register (SSR)
Page
542
564
611
617
Revision (See Manual for Details)
Figure 12.6 amended
TCNT
Overflow signal
(internal signal)
OVF
Table 13.3 amended
Description amended
Features of the Smart Card interface supported by the
H8S/2350 Group are as follows.
Bit 4 ERS
Bit table amended
Bit Rate
(bit/s)
19200
31250
38400
Bit 4
ERS
0
1
Description
Indicates that data was received normally and no error signal was sent
[Clearing conditions]
Indicates that an error signal was sent from the receiving side showing that a parity
error was detected
[Setting condition]
When the low level of the error signal is sampled
Upon reset, and in standby mode or module stop mode
When 0 is written to ERS after reading ERS = 1
n
0
0
0
= 7.3728 MHz
11
6
5
N
H'FF
—
0. 00
Error
(%)
0.00
H'00
(Initial value)
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