KFM2G16Q2M-DEB5 SAMSUNG [Samsung semiconductor], KFM2G16Q2M-DEB5 Datasheet - Page 56

• Manufacturer Part Number: KFM2G16Q2M-DEB5
• Description: MuxOneNAND FLASH MEMORY
• Manufacturer: SAMSUNG [Samsung semiconductor]

MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
2.8.22 Interrupt Status Register F241h (R/W)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes
low if INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
This Read/Write register shows status of the MuxOneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
INT
15
sets itself to ’1’
sets itself to ’1’
sets itself to ’1’
clears to ’0’
clears to ’0’
clears to ’0’
Status
Status
Status
14
13
One or more of RI, WI, RSTI and EI is set to ’1’,
(0000h, 0013h, Load Data into Buffer, or boot
or 0065h, 0023h, 0071h, 002A and 002C com-
At the completion of an Program Operation
Cold/Warm/Hot reset is being performed
Cold/Warm/Hot reset is being performed
Cold/Warm/Hot reset is being performed
At the completion of an Load Operation
Reserved(0000000)
12
’0’ is written to this bit, or
’0’ is written to this bit, or
’0’ is written to this bit, or
(0080h, 001Ah, 001Bh)
mands are completed
11
Conditions
Conditions
Conditions
is done)
10
9
8
56
RI
7
Cold
Cold
Cold
1
1
0
Default State
Default State
WI
Default State
6
Warm/hot
Warm/hot
EI
Warm/hot
5
1
0
0
RSTI
4
FLASH MEMORY
3
State
State
Valid
Valid
Valid
State
0
1
0
1
0
1
→
→
→
→
→
→
0
0
0
Reserved(0000)
1
0
1
0
1
0
2
Function
Function
Interrupt
Function
1
interrupt
interrupt
Pending
Pending
Pending
off
off
off
off
off
off
0