KFM2G16Q2M-DEB5 SAMSUNG [Samsung semiconductor], KFM2G16Q2M-DEB5 Datasheet - Page 39

• Manufacturer Part Number: KFM2G16Q2M-DEB5
• Description: MuxOneNAND FLASH MEMORY
• Manufacturer: SAMSUNG [Samsung semiconductor]

MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
2.8
2.8.1
Section 2.8 of this specification provides information about the MuxOneNAND1G registers.
This map describes the register addresses, register name, register description, and host accessibility.
F007h~F0FFh
F108h~F1FFh
F242h~F24Bh
F201h~F207h
F208h~F21Fh
F223h~F22Fh
F230h~F23Fh
(word order)
Address
F24Ch
F000h
F001h
F002h
F003h
F004h
F005h
F006h
F100h
F101h
F102h
F103h
F104h
F105h
F106h
F107h
F200h
F220h
F221h
F222h
F240h
F241h
Register Address Map
Registers
1E00Eh~1E1FEh
1E210h~1E3FEh
1E402h~1E40Eh
1E410h~1E43Eh
1E446h~1E45Eh
1E460h~1E47Eh
1E484h~1E496h
(byte order)
Address
1E00Ah
1E00Ch
1E20Ah
1E20Ch
1E20Eh
1E000h
1E002h
1E004h
1E006h
1E008h
1E200h
1E202h
1E204h
1E206h
1E208h
1E400h
1E440h
1E442h
1E444h
1E480h
1E482h
1E498h
Controller Status
Manufacturer ID
Data Buffer size
Boot Buffer size
Start address 1
Start address 2
Start address 3
Start address 4
Start address 5
Start address 6
Start address 7
Start address 8
Configuration 1
Configuration 2
Block Address
Technology
Start Buffer
Version ID
Command
Amount of
Device ID
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Interrupt
System
System
buffers
Name
Start
Access
39
R, R/W
Host
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
Manufacturer identification
Device identification
N/A
Data buffer size
Boot buffer size
Amount of data/boot buffers
Info about technology
Reserved for user
Chip address for selection of NAND
Core in DDP & Block address
Chip address for selection of BufferRAM in DDP
Destination Block address for Copy back program
Destination Page & Sector address for Copy
back program
N/A
N/A
N/A
NAND Flash Page & Sector address
Reserved for user
Buffer Number for the page data transfer to/from the
memory and the start Buffer Address
The meaning is with which buffer to start and how many
buffers to use for the data transfer
Reserved for user
Reserved for vendor specific purposes
Host control and memory operation commands
memory and Host Interface Configuration
N/A
Reserved for user
Reserved for vendor specific purposes
Controller Status and result of memory operation
Memory Command Completion Interrupt Status
Reserved for user
Start memory block address in Write Protection mode
FLASH MEMORY
Description