KFM2G16Q2M-DEB5 SAMSUNG [Samsung semiconductor], KFM2G16Q2M-DEB5 Datasheet - Page 48
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KFM2G16Q2M-DEB5
Manufacturer Part Number
KFM2G16Q2M-DEB5
Description
MuxOneNAND FLASH MEMORY
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.KFM2G16Q2M-DEB5.pdf
(124 pages)
- Current page: 48 of 124
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NOTE:
1) 0080h programs both main and spare area, while 001Ah programs only spare area. Refer to chapter 5.8 for NOP limits in issuing these commands.
When using 0080h and 001Ah command, Read-only part in spare area must be masked by FF. (Refer to chapter 2.7.2)
2)’Reset MuxOneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state as the warm reset(=reset by RP pin).
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
2.8.18 Command Register F220h (R/W)
This Read/Write register describes the operation of the MuxOneNAND interface.
Note that all commands should be issued right after INT is turned from ready state to busy state. (i.e. right after 0 is written to INT reg-
ister.) After any command is issued and the corresponding operation is completed, INT goes back to ready state. (00F0h and 00F3h
may be accepted during busy state of some operations. Refer to the rightmost column of the command register table below.)
F220h, default = 0000h
15
14
001Ah
001Bh
002Ah
002Ch
00B0h
00F0h
00F3h
0000h
0013h
0080h
0023h
0071h
0094h
0095h
0030h
0065h
CMD
13
12
11
Load single/multiple sector data unit into buffer
Load single/multiple spare sector into buffer
Program single/multiple sector data unit from buffer
Program single/multiple spare data unit from buffer
Copy back Program operation
Unlock NAND array a block
Lock NAND array a block
Lock-tight NAND array a block
Erase Verify Read
Block Erase
Multi-Block Erase
Erase Suspend
Erase Resume
Reset NAND Flash Core
Reset MuxOneNAND
OTP Access
10
9
2)
8
Command
48
Operation
7
6
5
1)
4
FLASH MEMORY
3
2
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
00F0h, 00F3h
during busy
Acceptable
command
1
-
-
-
-
-
0
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