HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 790

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

21.3.2
Table 21.6 Control Signal Timing
Conditions: V
Item
RES rise and fall time
RES pulse width
NMI reset setup time
NMI reset hold time
NMI rise and fall time
RES setup time*
NMI setup time*
IRL3–IRL0 setup time*
NMI hold time
IRL3–IRL0 hold time*
BRLS setup time
BRLS hold time
BGR delay time
Bus tri-state delay time
Bus buffer on time
Note: * The RES, NMI, and IRL3–IRL0 signals are asynchronous inputs. If the setup times shown
here are observed, a transition is judged to have occurred at the fall of the clock; if the
setup times cannot be observed, recognition may be delayed until the next fall of the clock.
Control Signal Timing
V
CC
SS
= PV
= PLLV
SS
= PLLV
CC
= 3.3 V ±0.3 V, PV
SS
= 0 V, Ta = –20 to +75°C
Symbol
tRESr,
tRESf
tRESW
tNMIRS
tNMIRH
tNMIr,
tNMIf
tRESS
tNMIS
tIRLS
tNMIH
tIRLH
tBLSS
tBLSH
tBGRD
tBOFF
tBON
CC
Min
—
20
tPcyc + 10
tPcyc + 10
—
3tEcyc + 40 —
40
30
20
20
7
8
—
0
0
= 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV
Max
200
—
—
—
200
—
—
—
—
—
—
15
35
35
Unit
ns
tPcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
Figure
21.8
21.9
21.10
V
CC
,
781