HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 432

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

10.2.3
The E-DMAC receive request register issues receive directives to the E-DMAC.
Bits 31 to 1—Reserved: These bits should only be written with 0.
Bit 0—Receive Request (RR): When 1 is written to this bit, the E-DMAC reads a descriptor, and
then transfers receive data to the buffer in response to receive requests from the EtherC.
Bit 0: RR
0
1
Notes: In order to receive a frame in response to a receive request, the receive active bit in the
Initial value:
Initial value:
receive descriptor must be set to “active” beforehand.
1. When the receive request bit is set, the E-DMAC reads the relevant receive descriptor.
2. If the receive active bit in the descriptor has the “active” setting, the E-DMAC prepares
3. When one receive buffer of data has been received, the E-DMAC reads the next
E-DMAC Receive Request Register (EDRRR)
for a receive request from the EtherC.
descriptor and prepares to receive the next frame. If the receive active bit in the
descriptor has the “inactive” setting, the RR bit is cleared and operation of the receive
DMAC is halted.
R/W:
R/W:
Bit:
Bit:
Description
After frame reception is completed, the receiver is disabled
A receive descriptor is read, and transfer is enabled
31
—
—
—
—
0
7
0
30
—
—
—
—
0
6
0
29
—
—
—
—
0
5
0
. . .
. . .
. . .
. . .
—
—
4
0
11
—
—
—
—
0
3
0
10
—
—
—
—
0
2
0
—
—
—
—
9
0
1
0
R/W
RR
—
—
8
0
0
0
417