HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 511

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Transfer Width
Transfer bus mode
Transfer address mode
Notes: 1. Do not set a 16-byte unit; operation is not guaranteed if this setting is made.
Transfer Width
Transfer bus mode
Transfer address mode
Note: * Edge detection must be set when burst mode is selected as the transfer bus mode.
496
Clock
Bus cycle
DREQn
(Active high)
DACKn
(Active high)
RAS
CAS
RD/WR
WEn/DQMxx
SDRAM one-cycle write
When a one-cycle write is performed to synchronous DRAM, the DACKn signal is
synchronized with the rising edge of the clock. A request by the request signal is accepted
while the clock is high during DACKn output.
2. Cycle-steal mode must be set when DREQ is level-detected.
Figure 11.28 (a) Synchronous DRAM One-Cycle Write Timing
CPU
1st
acceptance
Byte/Word/Longword
Transfer*
Cycle-steal mode*
Single mode
Byte/Word/Longword
Transfer
Burst mode
Single mode
Blind zone
CPU
1
2nd
acceptance
DACK1
DMAC1
2
DREQn Detection
Method
DACKn output timing
Bus cycle
DREQn Detection
Method
DACKn output timing
Bus cycle
CPU
3rd
acceptance
DACK2
DMAC2
CPU
Level Detection
Write DACK
Basic bus cycle
Level Detection*
Write DACK
Basic bus cycle
4th
acceptance
DACK3
DMAC3
CPU
. . . .