HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 320

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.5.7
Bank Active Function
A synchronous DRAM bank function is used to support high-speed accesses of the same row
address. When the RASD bit in MCR is set to 1, read/write accesses are performed using
commands without auto-precharge (READ, WRIT). In this case, even when the access is
completed, no precharge is performed. When accessing the same row address in the same bank, a
READ or WRIT command can be called immediately without calling an ACTV command, just
like the RAS down mode of the DRAM’s high-speed page mode Synchronous DRAM is divided
into two banks, so one row address in each can stay active. When the next access is to a different
row address, a PRE command is called first to precharge the bank, and access is performed by an
ACTV command and READ or WRIT command in order, after the precharge is completed. With
successive accesses to different row addresses, the precharge is performed after the access request
occurs, so the access time is longer. When writing, performing an auto-precharge means that no
command can be called for t
+ t
cycles after a WRITA command is called. When the bank
RWL
AP
active mode is used, READ or WRIT commands can be issued consecutively if the row address is
the same. This shortens the number of cycles by t
+ t
for each write. The number of cycles
RWL
AP
between the issue of the precharge command and the row address strobe command is determined
by the TRP1, TRP0 in MCR.
Whether execution is faster when the bank active mode is used or when basic access is used is
determined by the proportion of accesses to the same row address (P1) and the average number of
cycles from the end of one access to the next access (t
). When tA is longer than t
, the delay
A
AP
waiting for the precharge during a read becomes invisible. If t
is longer than t
+ t
, the
A
RWL
AP
delay waiting for the precharge also becomes invisible during writes. The difference between the
bank active mode and basic access speeds in these cases is the number of cycles between the start
of access and the issue of the read/write command: (t
+ t
)
(1 – P1) and t
,
RP
RCD
RCD
respectively.
The time that a bank can be kept active, t
, is limited. When the period will be provided by
RAS
program execution, and it is not assured that another row address will be accessed without a hit to
the cache, the synchronous DRAM must be set to auto-refresh and the refresh cycle must be set to
the maximum value t
or less. This enables the limit on the maximum active period for each
RAS
bank to be ensured. When auto-refresh is not being used, some measure must be taken in the
program to ensure that the bank does not stay active for longer than the prescribed period.
Figure 7.24 (a) and (b) show burst read cycles that is not an auto-precharge cycle, figure 7.25 (a)
and (b) show burst read cycles to a same row address, figure 7.26 (a) and (b) show burst read
cycles to different row addresses, figure 7.27 shows a write cycle without auto-precharge, figure
7.28 shows a write cycle to a same row address, and figure 7.29 shows a write cycle to different
row addresses.
In figure 7.25, a cycle that does nothing, Tnop, is inserted before the Tc cycle that issues the
READ command. Synchronous DRAMs have a 2 cycle latency during reads for the DQMxx
signals that specify bytes. If the Tc cycle is performed immediately without inserting a Tnop
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