HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 489

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 11.6 Selecting On-Chip Peripheral Module Request Mode with the AR and RS Bits
AR
0
Note: * Do not perform transfers between on-chip peripheral modules.
For outputting transfer request from the SCIF, SIO, and TPU, the corresponding interrupt enable
bits must be set to output the interrupt signals. Note that transfer request signals from on-chip
peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as
well. When an on-chip peripheral module is specified as the transfer request source, set the
priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller
(INTC) at or below the levels set in the I3–I0 bits of the CPU’s status register so that the CPU
does not accept the interrupt request signal.
With the DMA transfer request signals in table 11.6, when DMA transfer is performed a DMA
transfer request (interrupt request) from any module will be cleared at the first transfer.
474
RS4 RS3 RS2 RS1 RS0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
DMA Transfer
Request
Source
SCIF channel 1
receiver
SCIF channel 1
transmitter
SCIF channel 2
receiver
SCIF channel 2
transmitter
TPU channel
0A
TPU channel
0B
TPU channel
0C
TPU channel
0D
SIO channel 0
receiver
SIO channel 0
transmitter
SIO channel 1
receiver
SIO channel 1
transmitter
SIO channel 2
receiver
SIO channel 2
transmitter
DMA
Transfer
Request
Signal
RXI
TXI
RXI
TXI
TGI0A
TGI0B
TGI0C
TGI0D
RDFI
TDEI
RDFI
TDEI
RDFI
TDEI
Transfer*
Source
SCFRDR1 Any
Any
SCFRDR2 Any
Any
Any
Any
Any
Any
SIRDR0
Any
SIRDR1
Any
SIRDR2
Any
Transfer*
Destina-
tion
SCFTDR1 Cycle-
SCFTDR2 Cycle-
Any
Any
Any
Any
Any
SITDR0
Any
SITDR1
Any
SITDR2
Bus
Mode
Cycle-
steal
steal
Cycle-
steal
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
Cycle-
steal
DREQ
Setting
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low
Edge,
active-low