HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 180

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

As table 5.5 shows, between two and four on-chip peripheral modules are assigned to each
interrupt priority level setting register. Set the priority levels by setting the corresponding 4-bit
groups with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level 0 (the
lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to the
same bits (DMAC0 and DMAC1, or WDT and BSC refresh control unit), those two modules have
the same priority. A reset initializes IPRA–IPRE to H'0000. They are not initialized in standby
mode.
5.3.6
Vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the WDT
interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is
initialized to H'0000 by a reset. It is not initialized in standby mode.
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Watchdog Timer (WDT) Interval Interrupt Vector Number 6 to 0 (WITV6–
WITV0): These bits set the vector number for the interval interrupt (ITI) of the watchdog timer
(WDT). There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Bus State Controller (BSC) Compare Match Interrupt Vector Number 6 to 0
(BCMV6–BCMV0): These bits set the vector number for the compare match interrupt (CMI) of
the bus state controller (BSC). There are seven bits, so the value can be set between 0 and 127.
162
Initial value:
Initial value:
Vector Number Setting Register WDT (VCRWDT)
R/W:
R/W:
Bit:
Bit:
15
—
—
0
R
7
0
R
BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0
WITV6
R/W
R/W
14
0
6
0
WITV5
R/W
R/W
13
0
5
0
WITV4
R/W
R/W
12
0
4
0
WITV3
R/W
R/W
11
0
3
0
WITV2
R/W
R/W
10
0
2
0
WITV1
R/W
R/W
9
0
1
0
WITV0
R/W
R/W
8
0
0
0