HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 280

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.2.4
Do not access a space other than CS0 until the settings for register initialization are completed.
Bits 15 to 8—Idles between Cycles for Areas 3 to 0 (IW31–IW00): These bits specify idle cycles
inserted between consecutive accesses to different CS spaces. Idles are used to prevent data
conflict between ROM or the like, which is slow to turn the read buffer off, and fast memories and
I/O interfaces. Even when access is to the same space, idle cycles must be inserted when a read
access is followed immediately by a write access. The idle cycles to be inserted comply with the
specification for the previously accessed space The set values below show the minimum number
of idle cycles; more cycles than indicated by the Idles between Cycles setting may actually be
inserted.
IW31, IW21, IW11, IW01
0
1
Bits 7 to 0—Wait Control for Areas 3 to 0 (W31–W00)
When the CSn space is set as ordinary space, the number of CSn space waits can be specified
with Wn1 and Wn0.
Initial value:
Initial value:
Wait Control Register 1 (WCR1)
R/W:
R/W:
Bit:
Bit:
IW31
W31
R/W
R/W
15
1
7
1
IW30, IW20, IW10, IW00
0
1
0
1
IW30
W30
R/W
R/W
14
0
6
1
IW21
W21
R/W
R/W
13
1
5
1
IW20
W20
R/W
R/W
12
0
4
1
Description
No idle cycle
One idle cycle inserted
Two idle cycles inserted
Four idle cycles inserted
IW11
W11
R/W
R/W
11
1
3
1
IW10
W10
R/W
R/W
10
0
2
1
IW01
W01
R/W
R/W
9
1
1
1
Initial value)
IW00
W00
R/W
R/W
8
0
0
1
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