HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 374

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

When a cache miss occurs, the way for replacement is determined using the LRU information, and
the read address from the CPU is written in the address array for that way. Simultaneously, the
valid bit is set to 1. Since the 16 bytes of data for replacing the data array are simultaneously read,
the address on the cache address bus is output to the internal address bus and 4 longwords are read
consecutively. The access order is such that, for the address output to the internal address, the byte
address within the line is sequentially incremented by 4, so that the longword that contains the
address to be read from the cache comes last. The read data on the internal data bus is written
sequentially to the cache data array. One cycle after the last data is written to the cache data array,
it is also output to the cache data bus and the read data is sent to the CPU.
The internal address bus and internal data bus also function as pipelines, just like the cache bus
(figure 8.4).
358
data bus
data bus
EX: Instruction execution
MA: Memory access
WB: Write-back
address
address
pipeline
Internal
Internal
Cache
Cache
stage
CPU
bus
bus
EX
Address A
Cache tag comparison
MA
EX
Figure 8.4 Read Access in Case of a Cache Miss
Address A
+4
Address A
Address A
+4
+8
Data array write
Address B
Address A
Address A
+12
+8
Address A
Address A
+12
Address A
Address A
WB
MA