HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 672

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

16.2.4
Channel 0: TIER0
Channel 1: TIER1
Channel 2: TIER2
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has three TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset.
Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 6—Reserved: This bit is always read as 1. The write value should always be 0.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2.
In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: TCIEU
0
1
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4: TCIEV
0
1
660
Initial value:
Initial value:
Timer Interrupt Enable Register (TIER)
R/W:
R/W:
Bit:
Bit:
Description
Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
Description
Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
—
—
7
0
R
7
0
R
—
—
6
1
R
6
1
R
TCIEU
R/W
—
5
0
R
5
0
TCIEV
TCIEV
R/W
R/W
4
0
4
0
TGIED
R/W
—
3
0
3
0
R
TGIEC
R/W
—
2
0
2
0
R
TGIEB
TGIEB
R/W
R/W
1
0
1
0
(Initial value)
(Initial value)
TGIEA
TGIEA
R/W
R/W
0
0
0
0