HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 292

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

RTCOR is an 8-bit read/write register. The values of RTCOR and RTCNT are constantly
compared. When the values correspond, the compare match flag (CMF) in RTCSR is set and
RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register
(MCR) is set to 1, a refresh request signal occurs. The refresh request signal is held until refresh
operation is actually performed. If the refresh request is not processed before the next match, the
previous request becomes ineffective.
When the CMIE bit in RTCSR is set to 1, an interrupt request is sent to the controller by this
match signal. The interrupt request is output continuously until the CMF bit in RTCSR is cleared.
When the CMF bit clears, it only affects the interrupt; the refresh request is not cleared by this
operation. When a refresh is performed and refresh requests are counted using interrupts, a refresh
can be set simultaneously with the interval timer interrupt.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
7.3
7.3.1
Byte, word, and longword are supported as access units Data is aligned based on the data width of
the device Therefore, reading longword data from a byte-width device requires four read
operations The bus state controller automatically converts data alignment and data length between
interfaces. An 8-bit, 16-bit, or 32-bit external device data width can be connected by using the
mode pins for the CS0 space, or by setting BCR2 for the CS1–CS4 spaces. However, the data
width of devices connected to the respective spaces is specified statically, and the data width
cannot be changed for each access cycle. Figures 7.2 to 7.4 show the relationship between device
data widths and access units.
Initial value:
Access Size and Data Alignment
Connection to Ordinary Devices
R/W:
Bit:
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
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