HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 175

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.3
5.3.1
Interrupt priority level setting register A (IPRA) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRA is initialized to H'0000 by a
reset. It is not initialized in standby mode. Unless otherwise specified, ‘reset’ refers to both power-
on and manual resets throughout this manual.
Bits 15 to 12—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 11 to 8—Direct Memory Access Controller Interrupt Priority Level 3 to 0 (DMACIP3–
DMACIP0): These bits set the direct memory access controller (DMAC) interrupt priority level.
There are four bits, so levels 0–15 can be set. The same level is set for both two DMAC channels.
When interrupts occur simultaneously, channel 0 has priority.
Bits 7 to 4—Watchdog Timer (WDT) Interrupt Priority Level 3 to 0 (WDTIP3–WDTIP0): These
bits set the watchdog timer (WDT) interrupt priority level and bus state controller (BSC) interrupt
priority level. There are four bits, so levels 0–15 can be set. When WDT and BSC interrupts occur
simultaneously, the WDT interrupt has priority.
Bits 3 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Initial value:
Initial value:
Register Descriptions
Interrupt Priority Level Setting Register A (IPRA)
R/W:
R/W:
Bit:
Bit:
WDT
R/W
IP3
15
—
0
R
7
0
WDT
R/W
IP2
14
—
0
R
6
0
WDT
R/W
IP1
13
—
0
R
5
0
WDT
R/W
IP0
12
—
0
R
4
0
DMAC
R/W
IP3
11
—
0
3
0
R
DMAC
R/W
IP2
10
—
0
2
0
R
DMAC
R/W
IP1
—
9
0
1
0
R
DMAC
R/W
IP0
—
8
0
0
0
R
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