HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 176

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.3.2
Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 by a
reset. It is not initialized in standby mode.
Bits 15 to 12—Ethernet Controller Direct Memory Access Controller (E-DMAC) Interrupt
Priority Level 3 to 0 (E-DMACIP3–E-DMACIP0): These bits set the ethernet controller direct
memory access controller (E-DMAC) interrupt priority level. There are four bits, so levels 0–15
can be set.
Bits 11 to 8—Free-Running Timer (FRT) Interrupt Priority Level 3 to 0 (FRTIP3–FRTIP0): These
bits set the free-running timer (FRT) interrupt priority level. There are four bits, so levels 0–15 can
be set.
Bits 7 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
158
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Interrupt Priority Level Setting Register B (IPRB)
E-DMAC
R/W
IP3
15
—
R
0
7
0
E-DMAC
R/W
IP2
14
—
R
0
6
0
E-DMAC
R/W
IP1
13
—
R
0
5
0
E-DMAC
R/W
IP0
12
—
R
0
4
0
FRTIP3
R/W
11
—
R
0
3
0
FRTIP2
R/W
10
—
R
0
2
0
FRTIP1
R/W
—
R
9
0
1
0
FRTIP0
R/W
—
R
8
0
0
0