HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 253

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.3.2
1. If a CPU/instruction fetch/read/word setting is made in the break bus cycle register (BBRA,
2. In the case of an instruction for which pre-execution is set as the break condition, the break is
3. With the post-execution condition, an interrupt is generated after execution of the instruction
4. When an instruction fetch cycle is set for channel C or D, break data register C (BDRC) or
5. When an instruction fetch cycle is set, the start address at which that instruction is located
BBRB, BBRC, or BBRD), a CPU instruction fetch cycle can be selected as a break condition.
In this case, it is possible to specify whether the break is to be effected before or after
execution of the relevant instruction by means of the PCBA/PCBB/PCBC/PCBD bit in the
break control register (BRCR).
performed when it has been confirmed that the instruction has been fetched and is to be
executed. Consequently, a break cannot be set for an overrun-fetched instruction (an
instruction fetched but not executed in the event of a branch or interrupt transition). If a break
is set for the delay slot of a delayed branch instruction, or for the instruction following an
instruction for which interrupts are prohibited, such as LCD, an interrupt is generated before
execution of the next instruction at which interrupts are accepted.
set as the break condition, and before execution of the following instruction. As in 2 above, a
break cannot be set for an overrun-fetched instruction. If a break is set for a delayed branch
instruction, or for an instruction for which interrupts are prohibited, such as LCD, an interrupt
is generated before execution of the next instruction at which interrupts are accepted.
break data register D (BDRD) is ignored. Therefore, break data need not be set for an
instruction fetch cycle break.
should be set for the break. A break will not occur if a different address is set. Also, a break
will not occur if the address of the lower word of a 32-bit instruction is set.
Instruction Fetch Cycle Break
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