HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 67

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 2.6
SH7615 CPU
MOV.W
ADD
........
.DATA.W H'1234
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
However, Instructions such as AND manipulating bits, are executed directly in memory.
Delayed Branches: Such instructions as unconditional branches are delayed branch instructions.
In the case of delayed branch instructions, the branch occurs after execution of the instruction
immediately following the delayed branch instruction (slot instruction). This reduces pipeline
disruption during branching.
The branching operation of the delayed branch occurs after execution of the slot instruction.
However, with the exception of such branch operations as register updating, execution of
instructions is performed with the order of delayed branch instruction, then delayed slot
instruction.
For example, even if the contents of a register storing a branch destination address are modified by
a delayed slot, the branch destination address will still be the contents of the register before the
modification.
Table 2.7
SH7615 CPU
BRA
ADD
Multiplication/Multiply-Accumulate Operation: 16 16
to three cycles, and 16 16 + 64
cycles. 32 32
execute in two to four cycles.
TRGET
R1,R0
@(disp,PC),R1
R1,R0
Sign Extension of Word Data
Delayed Branch Instructions
64 multiplications and 32 32 + 64
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next operated
upon by an ADD instruction
Description
Executes an ADD before
branching to TRGET
64 multiply-accumulate operations execute in two to three
64 multiply-accumulate operations
Example of Conventional CPU
ADD.W
Example of Conventional CPU
ADD.W
BRA
32 multiplications execute in one
TRGET
R1,R0
#H'1234,R0
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