HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 570

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt
(TXI) request generation when, after serial transmit data is transferred from the transmit FIFO data
register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR
falls to or below the transmit trigger set number, and the TDFE flag is set to 1 in the serial status 1
register (SC1SSR).
Bit 7: TIE
0
1
Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger
Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-FIFO-data-full
interrupt (RXI) request and receive-error interrupt (ERI) request when, after serial receive data is
transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR),
the number of data bytes in SCFRDR reaches or exceeds the receive trigger set number, and the
RDF flag is set to 1 in SC1SSR.
Bit 6: RIE
0
1
Note: * RXI, ERI, and BRI interrupt requests can be cleared by reading 1 from the RDF or DR flag,
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE
0
1
Notes: 1. The TDRE flag in SC1SSR is fixed at 1.
set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing
the TIE bit to 0. When transmit data is written to SCFTDR using the on-chip DMAC, the
TDFE flag is cleared automatically.
the FER, PER, ORER, or ER flag, or the BRK flag, then clearing the flag to 0, or by clearing
the RIE bit to 0. With the RDF flag, read receive data from SCFRDR until the number of
receive data bytes is less than the receive trigger set number, then read 1 from the RDF
flag and clear it to 0.
2. Serial transmission is started when transmit data is written to SCFTDR in this state.
Serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit
is set to 1.
Description
Transmit-FIFO-data-empty interrupt (TXI) request disabled*
Transmit-FIFO-data-empty interrupt (TXI) request enabled
Description
Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request disabled
Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request enabled
Description
Transmission disabled*
Transmission enabled*
2
1
(Initial value)
(Initial value)
(Initial value)
557