HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 25

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 1.1
Item
Direct memory
access controller
(DMAC),
2 channels
On-chip RAM
Ethernet controller
direct memory
access controller
(E-DMAC),
2 channels
Features (cont)
Specifications
4-Gbyte address space, maximum 16M (16,777,216) transfers
Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length
Parallel execution of CPU instruction processing and DMA operation
possible in case of cache hit
Selection of dual address or single address mode
Cycle stealing or burst transfer
Relative channel priorities can be set (fixed mode/round robin mode)
DMA transfer is possible for the following devices:
External requests, DMA transfer requests from on-chip supporting
modules, auto requests
Interrupt request (DEIn) can be issued to CPU at end of data transfer
DACK used for DREQ sampling (however, there is always one overrun as
there is one acceptance before first DACK)
4-kbyte X-RAM
4-kbyte Y-RAM
Transfer possible between EtherC and external memory/on-chip memory
16-byte burst transfer possible
Single address transfer
Chain block transfer
32-bit transfer data width
4-Gbyte address space
Single address (data transfer rate of one transfer unit in one bus cycle)
Dual address (data transfer rate of one transfer unit in two bus cycles)
When synchronous DRAM is connected, 16-byte continuous read
When synchronous DRAM is connected, one-clock single address
External memory, on-chip memory, on-chip supporting modules
continuous write transfer is possible (dual)
transfer is possible up to 30 MHz
(excluding DMAC, BSC, UBC, cache)
7