HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 693

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Examples of Buffer Operation
TGR0B
TGR0A
H'0000
TGR0C
TGR0A
TIOCA
When TGR is an output compare register
Figure 16.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 16.4.5, PWM Modes.
TCNT value
Transfer
H'0200
H'0200
Figure 16.19 Example of Buffer Operation (1)
H'0200
H'0450
H'0450
H'0450
H'0520
H'0520
Time
681