s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 61

no-image

s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
s3c4510b01-QE80
Manufacturer:
BOURNS
Quantity:
400 000
Part Number:
s3c4510b01-QE80
Manufacturer:
SUNMNG
Quantity:
853
Part Number:
s3c4510b01-QE80
Manufacturer:
SAMSUNG
Quantity:
8 000
Part Number:
s3c4510b01-QER0
Manufacturer:
AMCC
Quantity:
156
Part Number:
s3c4510b01-QER0
Manufacturer:
SAMSUMG
Quantity:
20 000
Company:
Part Number:
s3c4510b01-QER0
Quantity:
58
Part Number:
s3c4510b01-QERO
Manufacturer:
Panasonic
Quantity:
12 000
Part Number:
s3c4510b01-QERO
Manufacturer:
SAMSUNG
Quantity:
16 615
S3C4510B
PSR TRANSFER (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented
using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 3-11.
These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of the
CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a general
register to be moved to the CPSR or SPSR_<mode> register.
The MSR instruction also allows an immediate value or register contents to be transferred to the condition code
flags (N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top four bits of
the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR.
OPERAND RESTRICTIONS
— In user mode, the control bits of the CPSR are protected from change, so only the condition code flags of the
— Note that the software must never change the state of the T bit in the CPSR. If this happens, the processor
— The SPSR register which is accessed depends on the mode at the time of execution. For example, only
— You must not specify R15 as the source or destination register.
— Also, do not attempt to access an SPSR in User mode, since no such register exists.
CPSR can be changed. In other (privileged) modes the entire CPSR can be changed.
will enter an unpredictable state.
SPSR_fiq is accessible when the processor is in FIQ mode.
INSTRUCTION SET
3-19

Related parts for s3c4510b