s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 232

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
THE MAC RECEIVE BLOCK
The MAC receive block is responsible for receiving data. It complies with the IEEE802.3 standard for carrier
sense multiple access with collision detection (CSMA/CD) protocol.
After it receives a packet, the receive block checks for a number of error conditions: CRC errors, alignment
errors, and length errors. Several of these checks can be disabled by setting bits in the appropriate control
registers. depending on the CAM status, the destination address and the receive block may reject an otherwise
acceptable packet. The MAC receive block consists of the following units:
— Receive FIFO, FIFO controller, and counters
— Receive BDI state machine
— Threshold logic and counters
— CAM block for address recognition
— Parallel CRC checker
— Receive state machine
The main components of the receive block are shown in Figure 7-4.
7-10
Rx_rd
Rx_rdy
Rx_EOF
Rx_keep
Rx_toss
Rx_load
CAM_hit#
Rx_DB [7:0]
and parity
Checker
Checker
CAM
CRC
BDI state
Machine
Receive
SYS_CLK Domain
Figure 7-4. MAC Receive Function Blocks
Read
address
and counter
Write FIFO
Thershold
controller
logic and
counter
9
MAC Receive
(16X10)
FIFO
Rx_CLK Domain
and counter
Write FIFO
controller
Write address
/WE
Check
Parity
Machine
Receive
Detect
State
SFD
RxD[3:0]
Rx_clk
Rx_DV
Rx_er
S3C4510B