s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 165

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C4510B
SYSTEM MANAGER
31
20
19
18 17
16
15
0
CLKCON
Clock Divided Value
[15:0] Clock diving value
If all bits are 0, non-divided clock is used. Only one bit
can be set in CLKCON[15:0]. That is, the clock diving
value is defined as 1,2,4,8,16,...
Internal system clock, f
= f
/(CLKCON+1)
MCLK
ICLK
[16] ROM bank 5 wait enable
0 = Disable ROM bank 5 wait.
1 = Enable ROM bank 5 wait.
[17] ROM bank 5 address/data bus MUX enable
0 = Normal operation
1 = Enable bus multiplexing
[19:18] MUX bus Address (tAC)
00 = 1 MCLK
01 = 2 MCLK
10 = 3 MCLK
[31] Test bit
This bit should be always 0.
Figure 4-7. Clock Control Register (CLKCON)
4-23

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