s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 259

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
MAC Transmit Control Register
To generate an interrupt after each packet, set the enable completion bit and all of the MAC error enable bits.
Using MAC transmit control register settings, you can also selectively enable interrupts for specific conditions.
MACTXCON
Bit Number
[31:15]
Registers
[10]
[11]
[12]
[13]
[14]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Transmit enable (TxEn)
Transmit halt request (TxHalt) Set this bit to halt transmission after completing any current
Suppress padding (NoPad)
Suppress CRC (NoCRC)
Fast back-off (FBack)
No defer (NoDef)
Send Pause (SdPause)
MII 10-Mb/s SQE test mode
enable (SQEn)
Enable underrun (EnUnder)
Enable deferral (EnDefer)
Enable no carrier (EnNCarr)
Enable excessive collision
(EnExColl)
Enable late collision
(EnLateColl)
Enable transmit parity
(EnTxPar)
Enable completion (EnComp)
Reserved
0XA008
Offset
Bit Name
Table 7-23. MAC Transmit Control Register Description
Table 7-22. MACTXCON Register
R/W
R/W
Set this bit to enable transmission. To stop transmission
immediately, clear the transmit enable bit to "0".
packet.
Set to not generate pad bytes for packets of less than 64 bytes.
Set to suppress addition of a CRC at the end of a packet.
Set this bit to use faster back-off times for testing.
Set to disable the defer counter. (The defer counter keeps
counting until the carrier sense (CrS) bit is turned off.)
Set this bit to send a pause command or other MAC control
packet. The send pause bit is automatically cleared when a
complete MAC control packet has been transmitted. Writing a
"0" to this register bit has no effect.
Set this bit to enable MII 10-Mb/s SQE test mode.
Set this bit to generate an interrupt if the MAC transmit FIFO is
empty during a transmission.
Set this bit to generate an interrupt if the MAC defers for
MAX_DEFERRAL time: "0" = 0.32768 ms at 100 Mb/s; "1" =
3.2768 ms at 10-Mb/s.
Set this bit to generate an interrupt if a carrier sense is not
detected while an entire packet is transmitted.
Set this bit to enable an interrupt if 16 collisions occur in the
same packet.
Set this bit to generate an interrupt if a collision occurs after 512
bit times (or 64 byte times).
Set this bit to generate an interrupt if a parity error is detected in
the MAC transmit FIFO.
Set this bit to generate an interrupt whenever the MAC
transmits or discards one packet.
Not applicable.
Transmit control
Description
Description
ETHERNET CONTROLLER
Reset Value
0x00000000
7-37