s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 228

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
S3C4510B
MEDIA INDEPENDENT INTERFACE (MII)
Transmit and receive blocks both operate using the MII, which was developed by the IEEE802.3 task force on
100-Mbit/s ethernet. This interface has the following characteristics:
— Media independence
— Multi-vendor points of interoperability
— Supports connection of MAC layer and physical layer entity (PHY) devices
— Capable of supporting both 100-Mbit/s and 10-Mbit/s data rates
— Data and delimiters are synchronous to clock references
— Provides independent 4-bit wide transmit and receive data paths
— Uses TTL signal levels that are compatible with common digital CMOS ASIC processes
— Supports connection of PHY layer and station management (STA) devices
— Provides a simple management interface
— Capable of driving a limited length of shielded cable
PHYSICAL LAYER ENTITY (PHY)
The physical layer entity, or PHY, performs all of the decoding/encoding on incoming and outgoing data. The
manner of decoding and encoding (Manchester for 10BASE-T, 4B/5B for 100BASE-X, or 8B/6T for 100BASE-T4)
does not affect the MII. The MII provides the raw data it receives, starting with the preamble and ending with the
CRC. The MII expects raw data for transmission, also starting with the preamble and ending with the CRC. The
MAC layer also generates jam data and transmits it to the PHY.
BUFFERED DMA INTERFACE (BDI)
The buffered DMA interface (BDI) supports read and write operations across the system bus. Two eight-bit buses
transfer data with optional parity checking. The system interface initiates data transfers. The MAC-layer controller
responds with a ready signal to accept data for transmission, or to deliver data which has been received. An end-
of-frame signal indicates the boundary between packets.
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