s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 218

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

I
I
The I
and a shift buffer register (IICBUF).
Control Status Register (IICCON)
The control status register for the I
6-8
2
2
C BUS SPECIAL REGISTERS
C BUS CONTROLLER
Bit Number
Register
IICCON
2
C-bus controller has three special registers: a control status register (IICCON), a prescaler register (IICPS),
[31:8]
[5:4]
[0]
[1]
[2]
[3]
[6]
[7]
Offset Address
Buffer flag (BF)
Interrupt enable (IEN)
Last received bit (LRB)
Acknowledge enable
(ACK)
COND1, COND0
Bus busy (BUSY)
Reset
Reserved
0xf000
Bit Name
Table 6-1. Control Status Register (IICCON)
2
C-bus, IICCON, is described in Table 6-2.
Table 6-2. IICCON Register Description
R/W
R/W
The BF bit is set when the buffer is empty in transmit mode or
when the buffer is full in receive mode. To clear the buffer, you
write a "0" to this bit. The BF bit is cleared automatically
whenever the IICBUF register is written or read. If you set BF bit
to one, the I
clear the BF bit to zero.
Setting the interrupt enable bit to "1" enables the I
interrupt.
The LRB bit is read only. It holds the value of the last received bit
over the I
acknowledgement. To check for slave acknowledgement, you
test the LRB.
The ACK bit is normally set to "1". This causes the I
controller to send an acknowledge automatically after each byte.
This bit must be "0" when the I
receiver mode and requires no further data to be received from
the slave transmitter. This causes a negative acknowledge on the
I
These bits control the generation of the start, Stop, and repeat
Start conditions: "00" = no effect, "01" = start, "10" = stop, and
"11" = repeat start.
This bit is a read-only flag that indicates when the I
use. A "1" indicates that the bus is busy. This bit is set or cleared
by a start or stop condition, respectively.
If "1" is written to the reset bit, the I
initial state.
Not applicable.
2
C-bus, which halts further reception from the slave device.
Control status register
2
C-bus. Normally, this bit will be the value of the slave
2
C -bus is stopped. To activate I
Description
Description
2
C-bus controller is operating in
2
C-bus controller is reset to its
2
C-bus, you should
0x00000000
2
Rest Value
C-bus
2
2
C-bus is in
C-bus
S3C4510B