s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 261

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
MAC Receive Control Register
To issue an interrupt after each packet is received, set the enable good bit and all of the error enable bits in the
MACRXCON register. You can also enable interrupts for specific conditions. Standard packet length values do
not include a preamble or a start frame delimiter (SFD).
NOTE: The frame lengths given above do not include preamble and start frame delimiter (SFD).
MACRXCON
Bit Number
[31:15]
Registers
[10]
[11]
[12]
[13]
[14]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Receive enable (RxEn)
Receive halt request (RxHalt)
Long enable (LongEn)
Short enable (ShortEn)
Strip CRC value (StripCRC)
Pass control packet (PassCtl)
Ignore CRC value
(IgnoreCRC)
Reserved
Enable alignment (EnAlign)
Enable CRC error
(EnCRCErr)
Enable overflow (EnOver)
Enable long error (EnLongErr) Set this bit to enable the long error interrupt. A long error
Reserved
Enable receive parity
(EnRxPar)
Enable Good (EnGood)
Reserved
0XA010
Offset
Bit Name
Table 7-27. MAC Receive Control Register Description
Table 7-26. MACRXCON Register
R/W
R/W
Set this bit to "1" to enable MAC receive operation. If "0", stop
reception immediately.
Set this bit to halt reception after completing the reception of
any current packet.
Set this bit to receive frames with lengths greater than 1518
bytes.
Set this bit to receive frames with lengths less than 64 bytes.
Set this bit to check the CRC, and then strip it from the
message.
Set this bit to enable the passing of control packets to a MAC
client.
Set this bit to disable CRC value checking.
Not applicable.
Set this bit to enable the alignment interrupt. An alignment
interrupt occurs when a packet is received whose length (in bits)
is not a multiple of eight, and whose CRC is invalid.
Set this bit to enable the CRC interrupt. A CRC interrupt occurs
when a packet is received whose CRC is invalid or if, during its
reception, the PHY asserts Rx_er.
Set this bit to enable the overflow interrupt. An overflow
interrupt is generated when a packet is received and the MAC
receive FIFO is full.
interrupt is generated when a frame longer than 1518 bytes is
received (unless the long enable bit is set).
Not applicable.
Set this bit to enable a receive parity interrupt if the MAC
receive FIFO detects a parity error.
Set this bit to enable the good (packet) interrupt upon error-free
reception of a complete data packet.
Not applicable.
Receive control
Description
Description
ETHERNET CONTROLLER
Reset Value
0x00000000
7-39