s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 155

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

S3C4510B
Table 4-9 and 4-10
Using little-endian and word access, Program/Data path between register and external memory
WA=Address whose LSB is 0,4,8,C
X=Don't care
CAS3-0/nWBE3-0=0 means active and 1 means inactive
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
Bit Num.
Internal SD Bus
External Address
Bit Num.
XDATA
Bit Num.
Ext. Memory Data
Timing Sequence
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
Bit Num.
Internal SD Bus
External Address
Bit Num.
XDATA
Bit Num.
Ext. Memory Data
Timing Sequence
Ext. Memory Type
Ext. Memory Type
Table 4-10. Word Access Load Operation with Little-Endian
Table 4-9. Word Access Store Operation with Little-Endian
Word
Word
abcd
abcd
abcd
abcd
abcd
abcd
abcd
abcd
abcd
abcd
31 0
31 0
31 0
31 0
31 0
31 0
31 0
31 0
31 0
31 0
WA
WA
WA
1st write
1st read
XXcd
XXcd
abcd
abcd
31 0
31 0
31 0
31 0
15 0
15 0
15 0
15 0
WA
WA
cd
cd
cd
cd
Half Word
Half Word
STORE (CPU Reg
abcd
abcd
31 0
LOAD (CPU Reg
31 0
WA
WA
2nd write
2nd read
WA + 2
abcd
abcd
abcd
abcd
31 0
31 0
31 0
31 0
WA
15 0
15 0
15 0
15 0
ab
ab
ab
ab
1st write
1st read
WA + 2
XXXd
XXXd
abcd
abcd
31 0
31 0
31 0
31 0
WA
7 0
7 0
7 0
7 0
d
d
d
d
External Memory)
External Memory)
2nd write
2nd read
WA + 1
XXcd
XXcd
abcd
abcd
31 0
31 0
31 0
31 0
WA
7 0
7 0
7 0
7 0
c
c
c
c
Byte
abcd
Byte
abcd
31 0
31 0
WA
WA
3rd write
3rd read
WA + 1
WA + 2
Xbcd
Xbcd
abcd
abcd
31 0
31 0
31 0
31 0
7 0
7 0
7 0
7 0
SYSTEM MANAGER
b
b
b
b
4th write
4th read
WA + 2
WA + 3
abcd
abcd
abcd
abcd
31 0
31 0
31 0
31 0
7 0
7 0
7 0
7 0
a
a
a
a
4-13