s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 244

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
ETHERNET CONTROLLER SPECIAL REGISTERS
The special registers used by the S3C4510B ethernet controller are divided into two main groups:
— BDMA control and status registers
— MAC control and status registers
BDMA CONTROL AND STATUS REGISTERS
All registers that contain a memory address must store the address in a word-aligned format.
NOTES:
1.
2.
7-22
BDMATXCON
BDMARXCON
BDMATXPTR
BDMARXPTR
BDMARXLSZ
BDMASTAT
CAM
BDMATXBUF
(1)
BDMARXBUF
(1)
For testing, you can read the BDMA Tx/Rx buffer directly. The BDMA receive buffer has a 64 word by 33 bit size.
The highest bit, [32], indicates the data frame boundary, as shown in the following illustration:
You can access the EOF bit by reading the address range, 0x9800-0x98FC (read into LSB bit 0).
Registers
0x98FC
0x9800
EOF (End of Frame); Boundary of frame data.
32
0x9100–0x917C
0x9200–0x92FC
0x9800–0x98FC
0x9900–0x99FC
31
0x900C
0x9000
0x9004
0x9008
0x9010
0x9014
Offset
Table 7-2. BDMA Control and Status Registers
Figure 7-11. End of Frame Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Buffered DMA transmit control register
Buffered DMA receive control register
Transmit frame descriptor start address
Receive frame descriptor start address
Receive frame maximum size
Buffered DMA status
CAM content (32 words)
BDMA transmit (Tx) buffer (64 words)
for test mode addressing only
BDMA receive (Rx) buffer (64 words)
for test mode addressing only
Description
0
0x99FC
0x9900
0xFFFFFFFF
0xFFFFFFFF
Reset Value
0x00000000
0x00000000
0x00000000
Undefined
Undefined
Undefined
Undefined
S3C4510B