s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 133

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s3c4510b

Manufacturer Part Number
s3c4510b
Description
16/32-bit Risc Microcontroller
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C4510B
FORMAT 16: CONDITIONAL BRANCH
OPERATION
The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition
codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4
bytes) ahead of the current instruction.
The THUMB assembler syntax is shown in the following table.
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
15
1
Assembler
BEQ label
BCC label
BGE label
BNE label
BCS label
BVS label
BVC label
BPL label
BLS label
BMI label
BHI label
THUMB
14
1
13
0
12
1
ARM Equivalent
Table 3-23. The Conditional Branch Instructions
BEQ label
BCC label
BGE label
BNE label
BCS label
BVS label
BVC label
BPL label
BLS label
BMI label
BHI label
11
Cond
[7:0] 8-bit Signed Immediate
[11:8] Condition
Figure 3-45. Format 16
Branch if Z set (equal)
Branch if Z clear (not equal)
Branch if C set (unsigned higher or same)
Branch if C clear (unsigned lower)
Branch if N set (negative)
Branch if N clear (positive or zero)
Branch if V set (overflow)
Branch if V clear (no overflow)
Branch if C set and Z clear (unsigned higher)
Branch if C clear or Z set (unsigned lower or same)
Branch if N set and V set, or N clear and V clear
(greater or equal)
8
7
SOffset 8
Action
INSTRUCTION SET
0
3-91

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