s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 248

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
Buffered DMA Receive Control Register
The buffered DMA receive control register, BDMARXCON, is described in Tables 7-5 and 7-6 below.
7-26
Bit Number
BDMARXCON
[13:12]
Register
[4:0]
[10]
[11]
[5]
[6]
[7]
[8]
[9]
BDMA Rx burst size
(BRxBRST)
BDMA Rx stop/skip frame by
owner bit (BRxSTSKO)
BDMA Rx memory address
inc/dec (BRxMAINC)
BDMA Rx every received
frame interrupt enable
(BRxDIE)
BDMA Rx Null list interrupt
enable (BRxNLIE)
BDMA Rx not owner interrupt
enable (BRxNOIE)
BDMA Rx maximum size over
interrupt enable (BRxMSOIE)
BDMA Rx Big/Little Endian
(BRxLittle)
BDMA Rx word alignment
(BRxWA)
Offset Address
0x9004
Table 7-6. BDMA Receive Control Register Description
Bit Name
Table 7-5. BDMA RXCON Register
R/W
R/W
(Word size + 1) of data bursts requested in BDMA mode. If
the BRxBRST is zero, the burst size is one word. If the
BRxBRST is 31, the burst size is 32 words.
This bit determines whether the BDMA Rx controller issues an
interrupt, if enabled, or skips the current frame and goes to the
next frame descriptor (assuming BDMA is not the owner).
This bit determines whether the address is incremented or
decremented. If this bit is set to "1", the address will be
incremented.
This bit enables the BDMA Rx every received frame interrupt
which is generated by the BDMA controller each time is moves
a complete data frame into memory.
This bit enables the BDMA Rx null list interrupt which indicates
that the receive frame descriptor start address pointer,
BDMARXPTR, in the BDMA Rx block has a null (0x00000000)
address.
This bit enables the BDMA Rx not owner interrupt when the
ownership bit of the current frame does not belong to the
BDMA controller, and if the BRxSTSKO bit is set.
This bit enables the BDMA Rx maximum size over interrupt
when the received frame size is larger than the value in
receive frame maximum size register.
This bit determines whether the data is stored in Little- or Big-
Endian format. If it is set to "1", word swapping will take place
between the receive buffer and the system data bus.
The Rx word alignment bits determine how many bytes are
invalid in the first word of each data frame. These invalid bytes
are inserted when the word is assembled by the BDMA
controller. "00" = No invalid bytes, "01" = 1 invalid byte, "10" =
2 invalid bytes, and "11" = 3 invalid bytes.
Buffered DMA receive control register
Description
Description
0x00000000
Rest Value
S3C4510B