s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 280

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

ETHERNET CONTROLLER
THE MII STATION MANAGER
The MDIO (management data input/output) signal line is the transmit and receive path for control/status
information for the station management entity, STA. The STA controls and reads the current operating status of
the PHY layer. The speed of transmit and receive operations is determined by the management data clock,
MDC.
The frame structure of the STA which writes command to control registers, or which reads the status register of a
PHY device, is shown Table 7-45. The PHY address is defined as the identification (ID) value of the various PHY
devices that may be concected to a single MAC. Register addresses can contain the ID value for up to 32 types
of PHY registers.
Turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the STA and
a PHY device. So that the STA can read the set value of a PHY device register, it must transmit the frame data,
up to a specific register address, to the PHY device. During the write time (which is an undirected transmission),
the STA transmits a stream of turn-around bits. As a result, by transmitting a write or read message to a PHY
device through the MDIO, the STA can issue a request to set the operation or to read the operation status.
As its response this message, the PHY device resets itself, sets loop-back mode, selects active/non-active auto-
negotiation process, separates the PHY and MII electrically, and determines whether or not to activate the
collision detection process.
When it receives a read command, the PHY reports the kind of PHY device it is, such as 100Base-T4, FDX
100base-X, HDX 100Base-X, 10-Mb/s FDX, or 10-Mb/s HDX.
7-58
Read (Status)
(Command)
Write
Preamble
11111111
11111111
(32 bits)
(32 bits)
Start of
Frame
Table 7-45. STA Frame Structure Description
01
01
Direction: STA to PHY
Operation
01 (write)
10 (read)
Code
Address
5 bits
5 bits
PHY
Register
Address
5 bits
5 bits
Turnaround
10 (2 bits)
Z0
Direction: PHY to STA
16 bits
(register
value)
16 bits
(register
value)
Data
S3C4510B
Idle
Z
Z