s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 215

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

2
S3C4510B
I
C BUS CONTROLLER
DATA TRSANSFER OPERATIONS
Data Byte Format
Every data byte that is put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per
transfer is unlimited. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first.
If the receiver cannot receive another complete byte of data until it has performed some other function (such as
servicing an internal interrupt), it can hold the clock line SCL Low to force the transmitter into a wait state. The
data transfer then continues when the receiver is ready for another byte of data and releases the SCL line.
Acknowledge Procedure
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulses must be generated by the
bus master. The transmitter releases the SDA line (High) during the acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge pulse so that it remains stable low during the
High period of this clock pulse.
Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte is received.
When a slave receiver does not acknowledge from the slave address, the slave must leave the data line high.
The master can then generate a stop condition to abort the transfer.
If a slave receiver acknowledges the slave address, but later in the transfer cannot receive any more data bytes,
the master must again abort the transfer. This is indicated by the slave not generating the acknowledge on the
first byte to follow. The slave leaves the data line high and the master generates the stop condition.
If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not
generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must then
release the data line to let the master generate the stop condition.
6-5