s3c4510b Samsung Semiconductor, Inc., s3c4510b Datasheet - Page 312

• Manufacturer Part Number: s3c4510b
• Description: 16/32-bit Risc Microcontroller
• Manufacturer: Samsung Semiconductor, Inc.

HDLC CONTROLLERS
HDLC GLOBAL MODE REGISTER
8-26
Number
[14:12] Data formats (DF)
[18:16] DPLL clock select
[10:8]
[7:6]
[11]
[15]
Bit
[0]
[1]
[2]
[3]
[4]
[5]
Registers
HMODEA
HMODEB
Multi-Frame in HTxFIFO
in DMA operation (MFF)
Reserved
Rx clock
inversion(RXCINV)
Tx clock
inversion(TXCINV)
Rx Little-Endian mode
(RxLittle)
Tx Little-Endian mode
(TxLittle)
Reserved
Tx preamble
length(TxPL)
Reserved
Reserved
(DPLLCLK)
Bit Name
0 7000
0 8000
Offset
Table 8-6. HMODEA and HMODEB Register
Table 8-7. HMODE Register Description
If this bit is set, more than one frame can be loaded into HTxFIFO. In this
case, the frame size may be less than the FIFO size.
Not applicable.
If this bit set to '0', the receive clock samples the data at the rising edge.
If this bit set to '1', the receive clock samples the data at the falling edge.
If this bit set to '0', the transmit clock shifts the data at the falling edge.
If this bit set to '1', the transmit clock shifts the data at the rising edge.
This bit determines whether the data is in Little- or Big-endian format.
HRXFIFO is in Little-endian. If this bit is set to '0', then the data on the
system bus should be in Big-endian. Therefore the bytes will be swapped
in Big- endian.
This bit determines whether Tx data is in Little or Big endian (TxLittle)
format. HTxFIFO is in Little-endian. If this bit is set to '1', the data on the
system bus is Little endian. If this bit is set to '0', the data on the system
bus is in Big-endian. (that is, the data bytes are swapped to be Little
endian format.)
Not applicable
These bits determine the length of preamble to be sent before the opening
flag when the TxPRMB bit is set in the control register.
000 1byte, 001 2bytes,and 111 8bytes will be sent.
Not applicable
When the DF bits are '000', data is transmitted and received in the NRZ
data format. When DF is '001', the NRZI (zero complement) data format is
selected. DF = '010' selects the FM0 data format, DF = '011' the FM1 data
format, and DF = '100' the Manchester data format.
Not applicable
Using this setting, you can configure the clock source for DPLL to one of
the following pins: TxC, RxC, MCLK, BRGOUT1, or BRGOUT2. To select
one of these pins, set the DPLLCLK bits to '000', '001', '010', '011', or '100',
respectively.
R/W
R/W
R/W
HDLC Mode register
HDLC Mode register
Description
Description
Reset Value
0 00000000
0 00000000
S3C4510B