sed1374 ETC-unknow, sed1374 Datasheet - Page 94

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 86
13.5 Turning Off BCLK Between Accesses
SED1374
X26A-A-001-02
Hardware Power Save
Software Power Save
(except LCDPWR)
Panel Interface
REG[03h] bits [1:0]
Output Signals
(CNF4 = Low)
or
LCDPWR
LCDPWR
(CNF4 = Hi)
RESET#
After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are
held ‘low’. Software initializes the chip (i.e. programs the registers) and then - as a last step
set - programs REG[03h] bits [1:0] to 11. This starts the power-up sequence as shown. The
power-up/power-down sequence delay is 127 frames.
The power-up/power-down sequence also occurs when exiting/entering Software Power
Save Mode.
BCLK may be turned off (held low) between accesses if the following rules are observed:
1. BCLK must be turned off/on in a glitch free manner
2. BCLK must continue for a period equal to [8T
3. BCLK must be present for at least one T
access (RDY# asserted or WAIT# deasserted).
00
Figure 13-1: Panel On/Off Sequence
power-up
0 frame
11
127 frames
power-down
BCLK
Power Save Mode
before the start of an access.
BCLK
00
+ 12T
Epson Research and Development
Hardware Functional Specification
MCLK
power-up
0 frame
] after the end of the
Vancouver Design Center
Issue Date: 99/04/29
11