sed1374 ETC-unknow, sed1374 Datasheet - Page 48

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Page 40
1. Ts
2. t1
3. t3
4. t6
5. t7
SED1374
X26A-A-001-02
Symbol
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
Sync Timing
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
= pixel clock period
= t3
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 4]Ts
=[(REG[08h] bits 4-0) x 8 + 13]Ts
Data Timing
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
min
- 9Ts
Frame Pulse
FPDAT[7:0]
Shift Pulse
Line Pulse
Line Pulse
Figure 7-13: Single Monochrome 8-Bit Panel A.C. Timing
MOD
Parameter
t5
t6
t7
t1
t14 + 4
note 2
note 3
note 4
note 5
t14
Min
23
t4
9
1
8
4
4
9
4
4
t8
t2
t12
1
t3
t13
Typ
Epson Research and Development
t11
Hardware Functional Specification
t9
2
t10
Max
Vancouver Design Center
Issue Date: 99/04/29
(note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts

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