sed1374 ETC-unknow, sed1374 Datasheet - Page 291

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
4.1.2 Using The Generic #1 Host Bus Interface
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 99/01/05
Figure 4-2: Typical Implementation of MC68328 to SED1374 Interface - Generic #1
If UDS and/or LDS are required for their alternate IO functions, then the MC68328 to
SED1374 interface may be implemented using the SED1374 Generic #1 host bus interface.
Note that in either case, the DTACK signal must be made available for the SED1374, since
it inserts a variable number of wait states depending upon CPU/LCD synchronization and
the LCD panel display mode. WAIT# must be inverted (using an inverter enabled by CS#)
to make it an active high signal and thus compatible with the MC68328 architecture. A
single resistor is used to speed up the rise time of the WAIT# (DTACK) signal when
terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to SED1374 using
the Generic #1 host bus interface.
MC68328
DTACK
D[15:0]
RESET
A[15:0]
CSB3
UWE
CLK0
LWE
OE
Vcc
470
WE0#
AB[15:0]
DB[15:0]
WAIT#
RD/WR#
RD#
BUSCLK
WE1#
RESET#
CS#
SED1374
X26A-G-007-02
SED1374
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