sed1374 ETC-unknow, sed1374 Datasheet - Page 45

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
7.3.3 Single Monochrome 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Hardware Functional Specification
Issue Date: 99/04/29
DRDY (MOD)
DRDY (MOD)
FPDAT[7:4]
FPFRAME
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPLINE
FPLINE
Figure 7-10: Single Monochrome 4-Bit Panel Timing
1-1
1-2
1-3
1-4
LINE1
1-6
1-7
1-8
1-5
LINE2
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
LINE3
LINE4
VDP
HDP
LINE239 LINE240
VNDP
1-317
1-318
1-319
1-320
HNDP
LINE1
LINE2
X26A-A-001-02
SED1374
Page 37