sed1374 ETC-unknow, sed1374 Datasheet - Page 292

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 14
4.2 SED1374 Hardware Configuration
4.3 MC68328 Chip Select Configuration
SED1374
X26A-G-007-02
CNF2
Pin Name
CNF0
CNF1
CNF2
CNF3
CNF4
SED1374
0
0
0
0
1
1
1
1
1
1
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show those configuration settings important to the MC68K #1 and
Generic #1 host bus interfaces.
The SED1374 requires a 64K byte address space for the display buffer and its internal
registers. To accommodate this block size, it is preferable (but not required) to use one of
the chip selects from groups A or B. Virtually any chip select other than CSA0 or CSD3
would be suitable for the SED1374 interface.
In the example interface, chip select CSB3 is used to control the SED1374. A 64K byte
address space is used with the SED1374 control registers mapped into the top 32 bytes of
the 64K byte block and the 40K bytes of display buffer mapped to the starting address of
the block. The chip select should have its RO (Read Only) bit set to 0, and the WAIT field
(Wait states) should be set to 111b to allow the SED1374 to terminate bus cycles externally.
= configuration for MC68328 using Generic #1 host bus interface
= configuration for MC68328 using MC68K #1 host bus interface
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
= configuration for MC68328 support
value on this pin at the rising edge of RESET# is used to configure: (1/0)
CNF1
0
0
1
1
0
0
1
1
1
1
Table 4-1: Summary of Power-On/Reset Options
Table 4-2: Host Bus Interface Selection
0
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
X
X
X
X
X
X
0
1
0
1
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Big Endian
Active high LCDPWR signal
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
Host Bus Interface
1
Epson Research and Development
Vancouver Design Center
Issue Date: 99/01/05