sed1374 ETC-unknow, sed1374 Datasheet - Page 382

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 8
2 Direct Connection to the Philips PR31500/PR31700
2.1 General Description
SED1374
X26A-G-012-01
ENDIAN
PR31500/PR31700
/CARD1WAIT
/CARD1CSH
/CARD1CSL
DCLKOUT
D[31:24]
D[23:16]
A[12:0]
/RD
/WE
ALE
In this example implementation the SED1374 occupies the PR31500/PR31700 PC Card slot #1.
The SED1374 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The
address bus of the PR31500/PR31700 PC Card interface is multiplexed and can be demultiplexed
using an advanced CMOS latch (e.g., 74ACT373). The direct connection approach makes use of the
SED1374 in its “Generic Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
The “Generic #2” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
Figure 2-1: SED1374 to PR31500/PR31700 Direct Connection
Latch
V
DD
Clock divider
pull-up
...or...
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Oscillator
System RESET
IO V
IO V
+3.3V
DD
DD
See text
EPSON Research and Development
BS#
RD/WR#
IO V
RD#
WE#
BHE#
CLKI
BCLK
AB[15:13]
AB[12:0]
DB[7:0]
WAIT#
RESET#
CS#
DB[15:8]
SED1374
DD
, CORE V
Vancouver Design Center
Issue Date: 98/11/09
DD