sed1374 ETC-unknow, sed1374 Datasheet - Page 47

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
7.3.4 Single Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Hardware Functional Specification
Issue Date: 99/04/29
DRDY (MOD)
DRDY (MOD)
FPDAT[7:0]
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
FPFRAME
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
FPLINE
FPLINE
FPSHIFT
Figure 7-12: Single Monochrome 8-Bit Panel Timing
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
LINE1
1-13
1-10
1-11
1-12
1-14
1-15
1-16
1-9
LINE2
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
LINE3
LINE4
VDP
HDP
LINE479 LINE480
VNDP
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
HNDP
LINE1
LINE2
X26A-A-001-02
SED1374
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