sed1374 ETC-unknow, sed1374 Datasheet - Page 104

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 8
2 Initialization
SED1374
X26A-G-002-02
Register
[0A]
[0B]
[0C]
[0D]
[01]
[02]
[03]
[04]
[05]
[06]
[07]
[08]
[09]
[0F]
[10]
1010 0000 (B0)
1110 1111 (EF)
0001 1110 (1E)
0010 0000 (20)
0000 0011 (03)
0010 0111 (27)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0010 0110 (26)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
Value (hex)
This section describes the register settings and steps needed to initialize the SED1374. The
first step toward initializing the SED1374 is to set the control registers. The SED1374 then
generates the proper control signals for the display. After setting the control registers, the
Look-up Table must be programmed with meaningful values. This section does not cover
setting Look-Up Table values. See Section 4 on page 14 of this manual for Look-up Table
programming details.
The following initialization, presented in table form, provides the sequences and values to
set the registers. The notes column comments the reason for the particular value being
written.
This example writes to all the control registers. In practice, it may be possible to write to
only a subset of the registers. When the SED1374 is first powered up all registers, unless
noted otherwise in the specification, are set to zero. This example programs these registers
to zero to establish a known state.
The initialization enables the SED1374 to control a panel with the following specifications:
• 320x240 color dual passive panel at 75Hz.
• Color Format 2, 8-bit data interface.
• 4 bit-per-pixel (bpp) - 16 colors.
• 25 MHz input clock (CLKI).
Select an passive, Single, Color panel with a data width of 4-bits
Select normal power operation
Horizontal display size = (Reg[04]+1)*8 = (39+1) * 8 = 320 pixels
FPLINE start position (not used by STN)
FPFRAME start position (not used by STN)
Select 4-bpp color depth and high performance.
Vertical display size = Reg[06][05] + 1
= 0000 0000 1110 1111 + 1 = 239 +1 = 240 lines
Horizontal non-display period = (Reg[08] + 4) * 8
Vertical non-display period = REG[0A] = 38 lines
MOD rate - not required for this panel
Screen 1 Start Address - set to 0 for initialization
Screen 2 Start Address - set to 0 for initialization
= (30 + 4) * 8 = 272 pixels
Table 2-1: SED1374 Initialization Sequence
Notes
Epson Research and Development
Programming Notes and Examples
Frame Rate Calculation
Frame Rate Calculation
Split Screen on page 30
Vancouver Design Center
See Also
Issue Date: 99/04/27