sed1374 ETC-unknow, sed1374 Datasheet - Page 416

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 12
4.2 SED1374 Hardware Configuration
4.3 Register/Memory Mapping
SED1374
X26A-G-013-01
CNF2
CNF0
CNF1
CNF2
CNF3
CNF4
1
Signal
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the 8-bit processor
interface. The endian must be selected based on the 8-bit processor used.
The SED1374 needs a 64K byte block of memory to accommodate its 40K byte display
buffer and its 32 byte register set. The starting memory address is located at 0000h of the
64K byte memory block while the internal registers are located in the upper 32 bytes of this
memory block. (i.e. REG[0]= FFE0h).
An external decoder can be used to decode the address lines and generate a chip select for
the SED1374 whenever the selected 64K byte memory block is accessed. If the processor
supports a general chip select module, its internal registers can be programmed to generate
a chip select for the SED1374 whenever the SED1374 memory block is accessed.
= required configuration for this application.
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
= configuration for 8-bit processor host bus interface
CNF1
1
Table 4-1: Configuration Settings
Low
Table 4-2: Host Bus Selection
CNF0
1
BS#
1
Big Endian
Active high LCDPWR signal
Generic #2, 16-bit
Host Bus Interface
High
Epson Research and Development
Interfacing to an 8-bit Processor
Vancouver Design Center
Issue Date: 99/05/04